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1/25 l9230 march 2003 this is preliminary information on a new product now in development or undergoing evaluation. details are subject to change wit hout notice. n operating supply voltage 5v to 28v n typical r dson = 150 m w for each output transistor (at 25c) n continous dc load current 5a (t case < 100 c) n output current limitation at typ. 6a n short circuit shut down for output currents over 8a n logic- inputs ttl/cmos-compatible n operating-frequency up to 30 khz n over temperature protection n short circuit protection n undervoltage disable function n diagnostic by spi or status-flag (configurable) n enable and disable input n so20 power package description the l9230 is an spi controlled h-bridge, designed for the control of dc and stepper motors in safety crit- ical applications and under extreme environmental conditions. the h-bridge is protected against over temperature and short circuits and has an under voltage lockout for all the supply voltages v s (main dc power sup- ply). all malfunctions cause the output stages to go tristate. the h-bridge contains integrated free-wheel diodes. in case of free-wheeling condition, the lowside tran- sistor is switched on in parallel of its diode to reduce the current injected into the substrate. switching in parallel is only allowed, if the voltage- level of the according output-stage is below the ground-level.in this case it must be ensured, that the upper transistor is switched off. powerso20 bare-die ordering numbers: l9230 L9230-DIE1 preliminary data spi controlled h-bridge block diagram in1 v s gnd out1 out2 in2 di en dms sf/sck ss si so logic undervoltage v s internal 5v supply overcurrent high-side overcurrent low-side gate control 1 gate control 2 over temperature maximum current limitation d01at470a
l9230 2/25 pin function pin connection (top view) n pin description 1 gnd ground 2 sck/sf spi-clock/status-flag 3 in1 input 1 4v s supply voltage 5 v s supply voltage 6 ou1 output 1 7 ou1 output 1 8 so serial out 9 si serial in 10 gnd ground 11 gnd ground 12 dms diagnostic-mode selection (+ supply voltage for spi-interface) 13 en enable 14 ou2 output 2 15 ou2 output 2 16 v s supply voltage 17 ss slave select 18 di disable 19 in2 input 2 20 gnd ground gnd si dms in1 v s ou1 v s ou1 so sck gnd 10 8 9 7 6 5 4 3 2 13 14 15 16 17 19 18 20 12 1 11 gnd d01at471 en ou2 v s ou2 ss di in2 gnd
3/25 l9230 absolute maximum ratings the integrated circuit must not be destroyed by use at the limit values. each limit value can be used, as long as no other limit is violated. voltage reference point: all values are, if not otherwise stated, relative to ground. direction of current flow: current flow into a pin is positive. rise-, fall- and delaytimes: if not otherwise stated, all rise times are between 10% and 90%, fall times between 90% and 10% and delay times at 50% of the relevant steps. thermal data symbol parameter test condition min. typ. max. unit v s supply voltage static destruction proof -1 40 v dynamic destruction proof t <0.5s (single pulse, tj < 85c) -2 40 v v li logic inputs in1, in2, di, en, ss, si, sck,dms -0.5 7 v i li logic inputs in1, in2, di, en, ss, si, sck,dms -20 ma v lo logic outputs sf, so r 3 10k w -0.5 7 v symbol parameter test condition min. typ. max. unit t j junction temperature dynamic t < 1 s -40 +150 +175 c c t stg storage temperature -55 +125 c t amb ambient temperature -40 +125 c r th j-case thermal resistance junction to case (2) 3 c/w t j_sd thermal shutdown junction temperature threshold 165 175 c electrical characteristcs ( t j = -40 to +150c; v s = 5 to 28v) symbol parameter test condition min. typ. max. unit power supply v s supply voltage static condition 5 28 v dynamic condition (t < 500ms) 40 v undervoltage shutdown (at least down to 2.5v) (1) 4.7 5 v switch off voltage 4.5 5 v switch on voltage 4.7 5 v hysteresis 200 mv i s supply current f = 0 khz, i o = 0 a f = 20khz, i o = 0 a 13 30 ma ma note: 1. for supply voltages down to 2.5v the output stages are in tristate condition and the status flag is set to low. below 2. 5v the device operates in undefined condition 2. guaranteed by design and package characterization
l9230 4/25 logic inputs v i logic input voltage in1, in2, di, en 1 1.5 2 v i i logic input current in1, in2, di v i 1v -200 -125 m a i en input current en v ien 3 2v 75 100 m a t dt detection time en, di 3 4 m s power outputs (out1, out2) r s switch on resistance ls r out-vs , v s > 5 v 150 250 m w switch on resistance hs r out-gnd, v s > 5 v 150 250 m w current limitation peak value controlled inductive load l = 0,8 to 5 mh resistive load r = 0,8 to 1.8 w |i ou | max |i ou | max switch-off current -40 c < t j < 165 c t j < 175 c 5.5 6 2.5 7.7 a a t a switch-off time (2) 12 17 22 m s t b blanking time (2) 811.515 m s t a /t b tracking (2) 1.4 1.5 1.6 |i ouk | short circuit detection current (1) see figure 1 5.5 11 a d |i ouk | short circuit current trecking (1) 1600 ma t reactivation time after internal shut down (2) overcurrent- or overtemperature shut down to reactivation of the output stage 1ms i l leakage current output stage switched off 1 ma v fd free-wheel diode forward voltage i o = 3a, v s = 0v 2 v t rr free-wheel diode reverse recovery time (2) 100 ns v sfhigh output?high (sf not set) (*) v s = 5v, r pull_up = 27k w 4.1 v |i ou | max switch off current tj = -40 to 165c 6 a tj = < 175c 2.5 a i sf output?high (sf not set) (2) v sf = 5v 20 m a i sf output?low (sf set) (3 ) v sf = 1v 300 m a v sf = 0.5v 100 m a v sf = 0.8v 500 m a electrical characteristcs ( t j = -40 to +150c; v s = 5 to 28v) (continued) symbol parameter test condition min. typ. max. unit
5/25 l9230 (*) for lower pull up resistances than 27k w the specified value of xxxv (minimum) is guaranteed by design note: 1. in case of sc outx to vs the switch off current is always higher than the start value of current regulation ( d |i ouk | = |i ouk | - |i oumax | 2. guaranteed by design 3. value is tested down to 6v. for supply voltage below 6v on increased current can be fed back in the device via a protection p ath timing f pwm frequency min. operating time 10 m s 2 30 khz f s switching frequency during current limitation 5 30 khz t don output on-delay in1 --> out1 or in2 --> out2 35 m s t doff output off-delay 3 5 m s t r , t f output rise-, fall time out1h--> out1l, out2h--> out2l, iout = 3 a out1l--> out1h, out2l--> out2h 0.2 0.4 1 m s t ddis disable delay time din --> outn, en --> outn 3 4 m s t dp power on delay time v s = on --> output stage active 15 ms delay time for fault detection 5 15 m s | d i| effect of reverse current at power supply 4,5v < v dms < 5,5v - i vs < 3a d i for i si , i so , i ss , i sck , i in1 , i in2 , i en ,i di 100 m a electrical characteristcs ( t j = -40 to +150c; v s = 5 to 28v) (continued) symbol parameter test condition min. typ. max. unit
l9230 6/25 figure 1. output delay time figure 2. disable delay time figure 3. output switching time 50% 10% 90% 50% t don t doff in n out n d01at472 50% 10% z t ddis di n out n d01at473 10% 90% 90% t f t r out n d01at474
7/25 l9230 figure 4. figure 5. typ 6.6a 6.6a >8a current limitation overcurrent load current detail a overcurrent detection t a = switch_off time in current limitation t b = current limitation blanking time t a t b control signal a status flag d01at475 range of overtemperature switch-off tj tolerance-range of temperature-dependent current-reduction 165c 6.6a 2.5a imax 175c temperature-depending current-limitation maximum rating for junction temperature for < 1s 175c overtemperature switch-off > 175c switch-off current in case of current limitation 6,6a 1,1a tj < 165c for 165c < tj < 175c the maximum current decreases from imax. = 6,6a 1,1a to imax. = 2,5a 1,1a.
l9230 8/25 spi interface the timing of l9230 is defined as follows: - the change at output (so) is forced by the rising edge of the sck signal. - the input signal (si) is taken over on the falling edge of the sck signal. - ss = active without any clocks at sck is not allowed - the data received during a writing access is taken over into the internal registers on the rising edge of the ss signal, if exactly 16 spi clocks have been counted during ss = active. figure 6. electrical characteristcs ( continued) symbol parameter test condition min. typ. max. unit input sck (spi clock input 4.5v < dms < 5.5v) v sckl low level 1 v v sckh high level 2 v d v sck hysteresis 0.1 0.4 v c sck input capacity 10 pf so si msb in bit (n-4)...1 lsb in bit (n-4)...1 1 4 5 6 sck ss 7 8 n = 16 9 10 3 2 bit (n-3) bit 0; lsb tristate bit (n-3) bit (n-2) 11 12 electrical characteristics (continued)
9/25 l9230 -i sck input current pull up current source connected to v s 20 50 m a input ss (slave select signal) v ssl low level l9230 is selected 1 v v ssh high level 2 v d v ss hysteresis 0.1 0.4 v c ss input capacity 10 pf -i ss input current pull up current source connected to vdd 20 50 m a input si (spi data input) v sil low level 1 v v sih high level 2 v d v si hysteresis 0.1 0.4 v c si input capacity 10 pf -i si input current pull up current source connected to vdd 20 50 m a output so (tristate output of the l9230 (spi output); on active reset (di) output so is in tristate.) v sol low level i so = 2ma 0.4 v v soh high level i so = -2ma v vdd - 0.75 v c so capacity capacity of the pin in tristate 10 pf i so leakage current in tristate -10 10 m a input dms (supply-input for the spi-inteface and selection pin for spi- or sf-mode) v i input voltage spi-mode status-flag-mode 3.5 0.8 v v i c input current spi-mode 10 ma timing t cyc cycle-time (referred to master) 200 ns t lead enable lead time (referred to master) 100 ns t lag enable lag time (referred to master) 150 ns symbol parameter test condition min. typ. max. unit electrical characteristics (continued)
l9230 10/25 t v data valid cl = 40pf data valid cl = 200pf (referred to l9230) 40 150 ns ns t su data setup time (referred to master) 50 ns t h data hold time (referred to master) 20 ns t dis disable time (referred to l9230) 100 ns t dt transfer delay (referred to master) 150 ns t sckh serial clock high time (referred to master) 50 m s t sckl access time (referred to master) 8.35 ns clock inactive before chipselect becomes valid 200 ns clock inactive after chipselect becomes valid 200 ns t rs rise-, fall time load on so 50pf 20 ns diagnostic diagnostic threshold (open load detection dms > 4,5v, en < 0,8v) v out1 v out2 load is available 0.8 0.8 v v v out1 v out2 load is missing 1 v s 0.8 v v i out2 -i out1 diagnostic current dms > 4.5v, en < 0.8v dms > 4.5v, en < 0.8v 700 1000 1000 1500 1300 2000 m a m a tracking diagnostic current i out1 / i out2 1.4 1.5 1.6 t d delay time 30 100 ms symbol parameter test condition min. typ. max. unit
11/25 l9230 truth table 1.) in case of undervoltage tristate and status-flag are reset automatically. 2.) whenever overcurrent or overtemperature is detected, the fault is stored (i.e. status-flag remains low). the tristate conditions and the status-flag 3) are reset via di or en. l = low h = high x = high or low z = high impedance (all output stage transistors are switched off in static state. for more inform. see next page ) overcurrent: i out1,2 >8,0 a overtemperature: t j >175 c undervoltage: v vs-gnd <5.0 v (at least down to 2,5v) 3.) if mode ?status-flag is selected (see 1.5) 4.) if mode ?spi-diagnosis is selected (see 1.5) pos. di en in1 in2 out1 out2 sf 3) spi 4) dia_reg 1. forward l h h l h l h see page 17 2. reverse l h l h l h h 3. free-wheeling low l h l l l l h 4. free-wheeling high l h h h h h h 5. disable hxxxzz l 6. enable x l x x z z l 7. in1 disconnected l h z x h x h 8. in2 disconnected l h x z x h h 9. di disconnected zxxxzz l 10. en disconnected x z x x z z l 11. current limit. active l h x x z z h 12. undervoltage 1.) xxxxzz l 13. overtemperature 2.) xxxxzz l 14. overcurrent 2.) xxxxzz l
l9230 12/25 description of the state ?z the state ?z has, depending on the previous operating condition different meaning. 1. dynamical i. e. the inductive load is current carrying and is switched off according to pos. 5, 6, 9, 10, 11, 12, 13, or 14 of the truth table a.) all output stage transistors are switched off. b.) the current flow is continued via the free wheeling diodes. c.) free wheeling is detected by a negative voltage-level at oun. d.) switch on of the parallel-transistor of the current carrying diode. f.) free wheeling is finshed, if the voltage-level on oun is positive again. 2. statical g.) all output-stages switched off. figure 7. zo current carryng i vs -i gnd v s - v s -vd s -v s i load v oun free wheeling high impedance d01at478 z
13/25 l9230 diagnostic the diagnosis-mode can be selected between spi-diagnosis and status-flag diagnosis. the choise of the diagnosis-mode is selected by the voltage-level on pin 12 (dms d iagnosis m ode s election). dms = gnd status-flag dms = vcc spi-diagnostic for the connection of pins si, so, ss and sck/sf see fig. 10 respectively fig. 11. status-flag the status-flag showes the condition ?tristate. at the following fault-cases the output-stages switches in tristate and set the status-flag from high to low. - short circuit of out1 or out2 against v s or gnd - short circuit between out1 and out2 - overcurrent - overtemperature - undervoltage on v s in cause of short circuit or overcurrent, the fault will be stored. the output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. if the voltage level changes from high to low on di or from low to high on en, the output stage switches on again and the status-flag is reset to high-level. in cause of overtemperature the fault will be stored. the output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. the voltage level changes from high to low on di or from low to high on en, the output stage switches on again and the status-flag is reset to high-level. in cause of undervoltage on v batt the output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is fallen. if the voltage has risen about the specified value again, the output stage switches on again and the status-flag is reset to high-level. the maximum current which can flow under normal operating conditions is limited to typical i max. = 6,6a . when the maximum current value is reached, the output stages are switched tristate for a fixed time. according to the time-constant the current decreases exponentially until the next switch-on occurs. at the end if the fixed time the output stage switches on again and the status-flag is reset to high-level.
l9230 14/25 spi-interface general discription the serial spi interface establishes a communication link between l9230 and the systems microcontroller. l9230 always operates in slave mode whereas the controller provides the master function. the maximum baud rate is 2 mbaud (200pf). applying an active slave select signal at ss l9230 is selected by the spi master. si is the data input (slave in), so the data output (slave out). via sck (serial clock input) the spi clock is provided by the master. in case of inactive slave select signal (high) the data output so goes into tristate. figure 8. depending on the application the first two bits of an instruction may be used to estabish an extended device-addressing. this gives the opportunity to operate up to 4 slave-devices sharing one common ss signal from the master-unit power supply of the spi-interface spi-logic and i/o-pins are alternativ supplied from dms or vcc internal, depending on which voltage is higher. that is why diagnosis of the en-/di-pins is always possible, even in case of missing h-bridge-power supply e.g. during ?vorlauf/nauchlauf. spi control: si ss state machine shift register clock counter control bits parity generator dms spi power supply dia_reg
15/25 l9230 characteristics of the spi interface 1) when dms is > 3,5v, the spi is active, independent of the state of en or di and the voltage on v s . during active reset conditions (dms < 3,5v) the spi is driven into its default state. when reset becomes inactive, the state machine enters into a waitstate for the next instruction. 2) if the slave select signal at ss is inactive (high), the state machine is forced to enter the waitstate, i.e. the state machine waits for the following instruction. 3) during active (low) state of the select signal ss the falling edge of the serial clock signal sck will be used to latch the input data at si. output data at so are driven with the rising edge of sck. further processing of the data according to the instruction ( i.e. modification of internal registers) will be triggered by the rising edge of the ss signal. (-> see note) 3 ) chipaddress: in order to establish the option of extended addressing the uppermost two bits of the instruction-byte ( i.e the first two si-bits of a frame ) are reserved to send a chipaddress. to avoid a busconflict the output so must stay high impedant during the addressing phase of a frame (i.e. until the addressbits are recognised as valid chipaddress). this tristate behavior should be realised in any case, regardless wether the extended addressoption is used or not. if the chipaddress does not match, the according access w ill be i gnored and so remains high impedant for the complete frame regardless which frametype is applied. 5) check byte: simultaneously to the receipt of an spi instruction l9230 transmitts a check byte via the output so to the controller. this byte indicates regular or irregular operation of the spi. it contains an initial bitpattern and a flag indicating an invalid instruction of the previous access. 6) on the read access the databits at the spi input si are rejected. 7) invalid instruction/access: an instruction is invalid, if one of the following conditions is fulfilled: - an unused instruction code is detected (see tables with spi instructions). - in case the previous transmission is not completed in terms of internal data processing. ( violation of the minimum access-time. ) if an invalid instruction is detected, any modifications on registers of l9230 are not allowed. in case an unused instruction code occured the databyte ff hex will be transmitted after having sent the check byte. in addition any access is invalid if the number of spi clock pulses (fa lling edge) counted during active ss differs from exactly 16 clock pulses (-> see note).
l9230 16/25 spi communication figure 9. reading access / 8 bit spi instruction the uppermost 2 bit of the instruction byte contains the chipadress. the individual chipadress is a mask-option and must be defined in accordance to the spi-members sharing on ss line. spi instruction-format spi instruction-bytes msb 76543210 0 0 instr4 instr3 instr2 instr1 insr0 insw bit name description 7,6 cpad1,0 chip adress (has to be 0, 0) 5-1 instr (4-0) spi instruction (encoding) 0 insw dont care spi instruction encoding description bit 7,6 cpad1,0 bit 5,4,3,2,1 instr(4...0) bit 0 rd_ident 00 00000 0 read identifier rd_version 00 00001 1 read version rd_dia 00 00100 1 read dia_reg all others no function spi instruction msb xxxx xxxx ss si verification byte msb data/8 bit msb so d01at480
17/25 l9230 reset of the diagnostic register dia_reg on the following conditions dia_reg is reset: - di high - en low - with the rising edge of the ss-signal after the spi-instruction rd_dia. - when the voltage on dms exceeds the threshold for detecting spi-mode. (after undervoltage condition) - undervoltage on v s (< 5,0v) sets bit 0 .... bit 3 of dia_reg to 0000. - if ub rises over about the undervoltage level, the bits of dia_reg are restored (when v s internal or dms > 3,5v) verification byte: msb 76543210 zz10101trans_f bit name description 0 trans_f bit = 1: error detected during previous transfer bit = 0: previous transfer was recognised as valid 1 fixed to high 2 fixed to low 3 fixed to high 4 fixed to low 5 fixed to high 6 send as high impedance 7 send as high impedance
l9230 18/25 diagnostics/encoding of failures description of the spi registers (spi instructions: rd_dia) description of dia_reg bit7 register: dia_reg 76543210 di ot currred currlim dia21 dia20 dia11 dia10 state of reset: ffh access by controller: read only bit name description 0 dia 10 diagnosis-bit1 of out1 1 dia 11 diagnosis-bit2 of out1 2 dia 20 diagnosis-bit1 of out2 3 dia 21 diagnosis-bit2 of out2 4 currlim is set to ?0 in case of current limitation 5 currred is set to ?0 in case of temperature dependet current limitation 6 ot is set to ?0 in case of overtemperature 7 di shows the wired-or state of the pins en and di encoding of the diagnostic bits of the output-stages out1 and out2 dia21 dia20 dia11 dia10 - - 0 0 short circuit over load (scol) - - 0 1 short circuit to battery on out1 (scb1) - - 1 0 short circuit to ground on out1 (scg1) - - 1 1 no error detected on out1 0 0 - - open load (ol) 0 1 - - short circuit to battery on out2 (scb2) 1 0 - - short circuit to ground on out2 (scg2) 1 1 - - no error detected on out2 0 0 0 0 undervoltage on pin ub en di dia_reg bit7 00 0 01 0 10 1 11 0
19/25 l9230 device identifier the ics identifier is used for production test purposes and features plug & play functionality depending on the systems software release. it is made up on a device-number and a revision number each one read-only acces- sible via standardised instructions. the device number is defines once to allow indentification of different ic-types by software. the revision number may be utilised to distinguish different states of hardware. the contents is divided into an upper 4 bit field reserved to define revisions correspondending to specific software releases. the lower 4 bit field is utilised to indentify the actual maskset. both (swr and msr) will start with 0000 b and are increased by 1 every time an according modification of the hardware is introduced. reading the ic identifier (spi instruction: rd_ident): reading the ic revision number (spi instruction: rd_version): ic identifier1 (device id) 76543210 id7 id6 id5 id4 id3 id2 id1 id0 bit name description 7...0 id(7...0) id-no.: 10100001 l9230 ics revision number 76543210 swr3 swr2 swr1 swr0 msr3 msr2 msr1 msr0 bit name description 7...4 swr(3...0) revision corresponding to software release: 0hex 3...0 msr(3...0) revision corresponding to maskset: 0hex
l9230 20/25 figure 10. application example with spi-interface figure 11. application example with status-flag m c voltage regulator power-on reset in1 dms gnd d01at481 ub v cc v batt reset in2 di sck ss so si en i.e. watch dog m p m out1 out2 m c voltage regulator power-on reset in1 dms 47k gnd d01at482 ub v cc v batt reset in2 di sf ss so si en i.e. watch dog m p m out1 out2
21/25 l9230 figure 12. application examples for overvoltage- and reverse-voltage protection esd-solidity the connection pins of the ic have to be protected against electrostatic discharge esd) by suitable integrated protection structures. the integrated circuit has to meet the demand of the ?human-body-model with v c = 4kv c = 100pf and r2 = 1,5k w (330 w for out1 and out2). thereby any defect or destruction of the integrated circuit must not occur. the protection structures realized to reach the esd-strength have to be coordinated. the esd-strength has to be verified by the test circuit given as below. figure 13. for the pins 4, 5, 6, 7, 14 and 15 u c = + 4kv r 1 = 100k w r 2 = 330 w c = 100pf number of pulses each pin: 18 frequency: 1hz arrangement and performance: the requirements of mil883d methode 3015 have to be fulfilled. h-bridge h-bridge version 1 reverse polarity protection via main relais version 2 reverse polarity protection via active diode main relais ignition switch battery battery v s v s v s < 40v v s < 40v d01at483 = v r1 r2 s2 s1 c out u s s3 (1) dc- voltmeter (2) d01at484
l9230 22/25 iso-pulses in the main-power-supply-system disturbance transients according to iso 7637-1 first edition 1990-06-01 may occur. by means of external components (see fig. 12) the following maximum ratings of the ic will not be exceeded. statical -1v ...... +40v dynamical for t < 500 ms -2v ...... +40v appendix a figure 14. out1 out2 load available 1 1 open load 1 0 sc -> gnd on out1 with load 0 0 sc detected on normal operation sc -> gnd on out2 with load 0 0 sc detected on normal operation sc -> ub on out1 with load 1 1 sc detected on normal operation sc -> ub on out2 with load 1 1 sc detected on normal operation sc -> gnd on out1 open load 0 0 ol not detected double fault sc -> gnd on out2 open load 1 0 ol detected sc -> ub on out1 open load 1 0 ol detected sc -> ub on out2 open load 1 1 ol not detected double fault 1.5 ma 1 ma out1 out2 in2 in1 vbatt int 5v
23/25 l9230 appendix b figure 15. voltage supply of spi-logic and en/di-logic spi- logic en/di- logic undervoltage on vbatt dms so si sck ss en di vbatt dms = gnd en/di-logic is supplied from internal vcc dms = vcc en/di-logic is supplied from dms (or int. vcc) output- stage failure and status output stage status en/di internal vcc
l9230 24/25 outline and mechanical data e a2 a e a1 pso20mec detail a t d 110 11 20 e1 e2 h x 45 detail a lead slug a3 s gage plane 0.35 l detail b r detail b (coplanarity) gc - c - seating plane e3 b c n n h bottom view e3 d1 dim. mm inch min. typ. max. min. typ. max. a 3.6 0.142 a1 0.1 0.3 0.004 0.012 a2 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 d (1) 15.8 16 0.622 0.630 d1 9.4 9.8 0.370 0.386 e 13.9 14.5 0.547 0.570 e 1.27 0.050 e3 11.43 0.450 e1 (1) 10.9 11.1 0.429 0.437 e2 2.9 0.114 e3 5.8 6.2 0.228 0.244 g 0 0.1 0.000 0.004 h 15.5 15.9 0.610 0.626 h 1.1 0.043 l 0.8 1.1 0.031 0.043 n 8? (typ.) s 8? (max.) t 10 0.394 (1) d and e1 do not include mold flash or protusions. - mold flash or protusions shall not exceed 0.15mm (0.006) - critical dimensions: e, g and a3. powerso20 0056635 jedec mo-166 weight: 1.9gr
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